/*
 * Copyright 2024 Hangzhou Yingyi Technology Co., Ltd
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *    http://www.apache.org/licenses/LICENSE-2.0

 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __RASPI_SYSREGS_H__
#define __RASPI_SYSREGS_H__

// ***************************************
// SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual.
// ***************************************
#define SCTLR_EL1_WFE_NORMAL				(1 << 18)
#define SCTLR_EL1_WFI_NORMAL				(1 << 16)
#define SCTLR_EL1_MMU_ENABLED               (1 << 0)

// enable I-Cache(bit 12) and D-Cache(bit 2)
#define SCTLR_EL1_CACHE_ENABLED ((1 << 2) | (1 << 12))

#define SCTLR_EL1_VALUE_MMU_DISABLED	(SCTLR_EL1_WFE_NORMAL | SCTLR_EL1_WFI_NORMAL)
#define SCTLR_EL1_VALUE_MMU_ENABLED		(SCTLR_EL1_WFE_NORMAL | SCTLR_EL1_WFI_NORMAL | SCTLR_EL1_MMU_ENABLED)
#define SCTLR_EL1_VALUE_MMU_CACHE_ENABLED                                      \
	(SCTLR_EL1_VALUE_MMU_ENABLED | SCTLR_EL1_CACHE_ENABLED)
#define SCTLR_EL2_VALUE				(0)

// ***************************************
// HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual.
// ***************************************

#define HCR_EL2_RW	    			(1 << 31)
#define HCR_EL2_IMO	    			(1 << 4)
#define HCR_EL2_SWIO	    		(1 << 1)
#define HCR_EL2_VALUE				(HCR_EL2_RW)

// ***************************************
// SCR_EL3, Secure Configuration Register (EL3), Page 2648 of AArch64-Reference-Manual.
// ***************************************

#define CPACR_EL1_TTA					(1 << 28)
#define CPACR_EL1_FPEN_TRAP_EL0_EL1  	(0 << 20)
#define CPACR_EL1_FPEN_TRAP_EL0		  	(1 << 20)
#define CPACR_EL1_FPEN_TRAP_NONE	  	(3 << 20)
#define CPACR_EL1_VALUE					(CPACR_EL1_FPEN_TRAP_NONE)

// ***************************************
// CPACR_EL1, Architectural Feature Access Control Register.
// ***************************************

#define SCR_RESERVED	    		(3 << 4)
#define SCR_RW				(1 << 10)
#define SCR_NS				(1 << 0)
#define SCR_VALUE	    	    	(SCR_RESERVED | SCR_RW | SCR_NS)

// ***************************************
// SPSR_EL3, Saved Program Status Register (EL3) Page 389 of AArch64-Reference-Manual.
// ***************************************

#define SPSR_MASK_ALL 		(7 << 6)
#define SPSR_ELxh			(5 << 0)
#define SPSR_EL2_VALUE		(SPSR_MASK_ALL | SPSR_ELxh)

#endif /* __RASPI_SYSREGS_H__ */
